(1) Technical Field
This disclosure relates to transceivers, and more specifically to methods and apparatus for switching between transmit mode and receive mode within a transceiver.
(2) Background
In many instances today, a single antenna is connected to a transceiver for both transmission and reception. FIG. 1 is a simplified illustration of some of the components of one such transceiver 100. The transceiver 100 includes an antenna 102 connected to the first port 104 of a three-port RF circulator 106. A three-port circulator has a relatively low impedance for signals between counter-clockwise adjacent ports and a relatively high impedance between clockwise adjacent ports. Accordingly, there is a low impedance path through the circulator from the first port 104 to the second port 108. Likewise, there is a relatively low impedance from the second port 108 to the third port 124 and from the third port 124 to the first port 104. However, in the other direction through the circulator, there is a relatively high impedance from the first port 104 to the third port 124, from the third port 124 to the second port 108 and from the second port to the first port 104.
The second port 108 of the circulator 106 is coupled to the receiver section 110 of the transceiver 100 and to a detector section 111. Looking first at the receiver section 110, the second port 108 of the circulator 106 is coupled to a first port of a “through switch” 112 within the receiver section 110. In some cases, the through switch 112 is a field effect transistor (FET), and the first signal port of the through switch 112 is the drain of the FET. The receiver section 110 further includes a direct current (DC) blocking capacitor 114, a low noise amplifier (LNA) 116, a shunt switch 118 and a bias control circuit 120. In the case in which the through switch 112 is an FET, the second signal port is the source of the FET of the through switch 112. In some cases, the drain and source of the FET of the through switch 112 are interchangeable. The source is coupled to first terminal of the DC blocking capacitor 114. A second terminal of the DC blocking capacitor 114 is coupled to the input of the LNA 116.
A first signal port of the shunt switch 118, which in some cases is the drain of a FET, is also coupled to the source of the through switch 112. The second signal port is the source of the FET shunt switch 118. The source is coupled to ground. In receive mode, the shunt switch 118 and the through switch 112 work together to couple signals from the antenna 102 to the input of the LNA 116. That is, by turning on the through switch 112 and turning off the shunt switch 118, signals received through the antenna 102 are routed from the first port 104 of the circulator 106 to the second port of the circulator 108. The signals then follow the low impedance path through the through switch 112. The relatively high impedance of the non-conducting (“OFF”) shunt switch blocks the signal from shunting to ground. It should be noted that throughout this disclosure, the term “on” is used to refer to the operational state of a FET or other switching device in which there is a low impedance between the drain and source (or in non-FET devices, between the switch terminals) Likewise, the term “off” is used to refer to the operational state in which a high impedance is presented between the switch terminals (e.g., drain and source).
Looking next at the detector section 111, a similar arrangement of switches 113, 115 provides a path from the second port 108 of the circulator 106 to a 50 ohm detector 117 within the detector section 111 when the switch 113 is on and the switch 115 is off. The same signal that turns on the shunt switch 118 of the receiver section 110 is coupled to the control port to turn on the switch 113 in the detector section 111. Likewise, the switches 112 and 115 are controlled by the same signal. Therefore, when the switch 112 in the receiver section 110 is off, the switch 115 in the detector section 111 is also off. Accordingly, either the LNA 116 of the receiver section 110 or the detector 117 of the detector section 111 is coupled to the second output of the circulator 106 at any particular time. More particularly, when the transceiver 100 is in receive mode, the LNA 116 of the receiver section 110 is coupled to the port 108 of the circulator 106 and the input to the detector 117 is shunted to ground. When the transceiver 100 is in transmit mode, the detector 117 is coupled to the port 108 of the circulator 106 and the input to the LNA 116 is shunted to ground. The 50 ohm detector 117 provides a proper load for the circulator 106.
Radio frequency (RF) signals traverse the relatively low impedance path through the DC blocking capacitor 114 and are applied to the input of the LNA 116. In the case shown in FIG. 1, the bias control circuit 120 provides DC bias to the input of the LNA 116. In some cases, a timing processor 126 determines when the transceiver 100 is in transmit mode and when the transceiver 100 is in receive mode. The timing processor 126 can be as simple as some circuitry in the modulator/demodulator of the transceiver for determining when data is ready to be sent. Alternatively, the timing processor 126 can be a more sophisticated programmable device that determines the mode of the transceiver 100 based on several factors. The timing processor 126 provides a control signal 128 to the bias control circuit 120. In some cases, the bias control circuit 120 provides a bias that is appropriate to the mode of the transceiver (e.g., transmit or receive), as indicated by the control signal 128. The through switch 112 is turned on by applying a mode control signal Von to the control port (e.g., the gate) of the through switch 112. In some cases, the signal Von is generated by the timing processor 126. An inverse mode control signal Von  that is the inverse of the signal Von is applied to the control port (e.g., the gate) of the shunt switch 118. Thus, when the through switch 112 is turned on, the shunt switch 118 is turned off (assuming both FETs 112, 118 are the same, i.e., either P-channel or N-channel FETs).
The transceiver 100 further includes a transmit amplifier 122 that is coupled to the third port 124 of the circulator 106. In transmit mode, the transmit amplifier 122 outputs a transmit signal that is coupled through the third port 124 of the circulator 106 to the first port 104 of the circulator 106. As noted above, the circulator 106 has a relatively high isolation between the input to the third port 124 and the output from the second port 108. Therefore, the power applied to the input port 124 is principally coupled to the antenna 102. Nonetheless, in order to protect the LNA 116, the through switch 112 disconnects the LNA 116 from the antenna 102. In addition, the shunt switch 118 further isolates the input of the LNA 116 by coupling the input of the LNA 116 to ground through the DC blocking capacitor 114 and the shunt switch 118. Any power that is inadvertently coupled to the second port 108 of the circulator is isolated from the input of the LNA 116 by the high impedance between the drain and the source of the through switch 112, which is off during transmit mode and also by the low impedance to ground presented by the shunt switch 118 which is on during transmit mode.
When implementing the through switch 112 and the shunt switch 118 as FET switches, the through switch 112 must be capable of sustaining a relatively high drain to source voltage without breaking down. Therefore, the through switch 112 must be relatively large. Typically, this is implemented by stacking several individual FETs together to form the through switch 112. The number of FETs that are stacked depends upon several factors, including the drain to source voltage that the switch 112 is designed to withstand. In some cases, the shunt switch 118 also comprises several stacked FETs.
Each FET of the through switch 112 has a capacitance Cgs between the gate and source. These capacitances Cgs are in parallel. Therefore, the capacitance Cgs of each FET sums to form a total capacitance between the control terminal of the through switch 112 and the input of the LNA 116. When the through switch 112 changes state from off to on, the voltage swings from −V to +V for a total swing of 2V. That voltage, multiplied by the capacitance Cgs, determines the charge Q that is applied to the input of the LNA 116. In light of the relatively large value of the capacitance Cgs, the charge Q applied to the input of the LNA 116 can be substantial. In some cases, it could increase the gate voltage at the LNA input to an unsafe value. In some cases, this large voltage can cause a breakdown of the input of the LNA 116.
FIG. 2 is graph showing the voltage Vg applied to the input of the LNA 116 at the time the transceiver transitions from transmit mode to receive mode. FIG. 2 also shows the transition of the state of the signals Von and Von. As can be seen in FIG. 2, prior to time t0, the DC component of the voltage Vg is at (or near) the transmit mode bias level (i.e., the voltage provided from the bias control circuit 120 to the LNA input during the transmit mode. Any RF component of the signal that is present is disregarded for the purpose of this analysis). At time t0, the signal Von begins to transition from a low state, Vlow to a high state, Vhigh. Since the signal Von  is the inverse of the signal Von, the signal Von  will also start to transition from a high state, Vhigh, to a low state, Vlow. Accordingly, the charge that has been stored in the capacitance Cgs of the through switch 112 will cause the voltage Vg to rise as the through switch 112 starts to conduct and the shunt switch 118 turns off. In addition, the bias control circuit 120 attempts to transition the bias voltage at the input of the LNA 116 to a receive mode bias level. The voltage Vg rises to a peak at time t1, primarily as a consequence of the charge stored in the capacitance Cgs of the through switch 112. Starting at time t1, the voltage Vg decreases until at time t2 the voltage Vg reaches the receive mode bias level established by the bias control circuit 120. Finally, at time t3, the voltage stabilizes at the desired receive mode bias level.
There are two principle problems with the current transceiver 100. The first is that the amount of charge stored in the capacitance Cgs of the through switch 112 can be sufficiently great that the voltage Vg at time t1 damages the LNA input (i.e., breaks through the gate of the input FET of the LNA 116). The second problem is that during the relatively long time between t0 and t3 the LNA bias is disturbed, leading to fluctuations in the operation of the LNA 116, such as increased non-linear behavior. That is, the amount of time it takes to stabilize Vg at the receive mode bias level, causes the operation of the LNA 116 to vary for an undesirable amount of time.
It can be seen that there is currently a need for a method and apparatus that reduces the risk of damage to the input of an LNA of a transceiver during transitions from transmit mode to receive mode. In addition, there is a need for a method and apparatus that reduces the amount of variation at the LNA output during the transition to receive mode. The present disclosure presents a method and apparatus that meets this need.